The present invention relates to switching state retention circuits of the kind permitting a switching state at the input thereof to appear at the output thereof only after an enabling signal has permitted such a result and, more particularly, such switching state retention circuits which are formed by use of a feedback loop path arrangement.
There are many uses in digital systems for D-type flip-flops, i.e. data latches. Such latches are used frequently to store a signal value representing data received at a data input for a duration of time after an enabling signal of a particular logic value has also been received at an enable input, This arrangement is useful, for instance, in permitting subsequent portions of the digital system to operate on a fixed value signal at the output of the latch even though further changes are occurring at the latch data input.
Such D-type flip-flops or data latches are commonly provided in monolithic integrated circuits, along with much other circuitry, for purposes of improving performance, reducing size and reducing cost. Monolithic integrated circuit structural features arising in the implementation of such circuits have been shrinking rapidly in size in recent years. Along with this shrinkage, the electrical currents and electrical charges formed and manipulated in integrated circuits based on these features have also been diminishing in value. As a result, charges generated by certain charge generating disturbances, which in larger feature integrated circuits would not be a problem, become sufficiently large to cause difficulties in smaller feature integrated circuits.
In voltage level state switching circuits, such as logic circuits or memory circuits including such data latch circuits, which are constructed using such smaller integrated circuit structures, such disturbance charges can be sufficient to cause switching from an existing logic state to another at points in the circuit where such charge is generated. The proper operation of the circuit could therefore be disturbed resulting in erroneous logic signals. Typically, such disturbances are local to the region near the disturbance and are temporary; thus such a disturbance is often termed a "single event upset." Also, though the disturbance cause may be temporary, the results of the disturbance may be stored and are subject to being propagated further in the system which may lead to longer term and more significant defects.
In a D-type flip-flop, or data latch, using a feedback path arrangement, a charge disturbance transient event can propagate around the feedback path arrangement back to the location of the disturbance. As a result, the feedback path arrangement can reinforce this disturbance to result in establishing a logic state change in the feedback loop.
A common source of such charge generating disturbances is particle radiation. Such particles impinging on a monolithic integrated circuit chip will have "interactions" with the semiconductor material lattice structure and electrons along the paths thereof through the integrated circuit semiconductor material. This will result, for the short duration of these interactions, in raising the energy of the electrons involved into the conduction band and leaving corresponding holes in the valence band. Should such electron-hole pairs be generated sufficiently close to a semiconductor pn junction, the electrons and holes so situated are subject to being collected by the action of electric fields in the region resulting from the voltage applied to such junction and because of diffusion toward such junction. The structure of transistor devices in monolithic integrated circuits, and the methods of operating both such devices and the circuits using them generally, is such that only reverse-biased pn junctions need to be considered to understand the effects of a radiation particle impinging thereabout
The electrons and corresponding holes will be separated by the electric fields near the reverse-biased junction with the electrons attracted to the positive voltage side of the junction and the holes being attracted, or repelled, into the portions of the semiconductor material on the other side of the junction. This separation of electrons and holes, in effect, provides a temporary current flow from the positive voltage side of the semiconductor pn junction to the opposite side of this junction or, in effect, a radiation induced leakage current.
This current will be comprised of an immediate drift current component for electrons and holes which are immediately subject to such electric fields. A further component of this current will be provided by those electrons and holes which subsequently, by diffusion, move to be within the influence of such electric fields. Such current flows have the effect of discharging an n-type conductivity region placed at a positive voltage with respect to a p-type conductivity region on the other side of the intervening junction so that junction is reversed-biased. Such a discharge current reduces this positive voltage. Conversely, such currents tend to charge a p-type conductivity region placed at a negative voltage with respect to an n-type conductivity region on the other side of an intervening semiconductor pn junction to reverse-bias that junction. Such a charging acts to reduce the negative voltage to thereby reduce the reverse-bias across said junction. Thus, in either situation, the charge generated by an impinging radiation particle would act in a manner to tend to reduce the magnitude of reverse-bias voltages provided across reverse-biased semiconductor pn junctions separating p-type conductivity and n-conductivity regions suffering such an impingement.
The effects of radiation particle impingement on regions of semiconductor material near a reverse-biased semiconductor pn junction are a bit less severe for complementary metal-oxide-semiconductor (CMOS) technology because either the n-channel metal-oxide-semiconductor field-effect transistor (MOSFET) or the p-channel MOSFET in each pair will be formed in a "well" or "tub" in the semiconductor material substrate, while the remaining member of the pair will be formed directly in the substrate. The devices provided directly in the substrate will have all of the risks for reverse-bias semiconductor junctions therein due to radiation particle impingement thereabout as were described above. However, the other devices formed in "wells" in the semiconductor material substrate will have some of the charge induced therein attracted by the fields at the semiconductor pn junction separating the well from the substrate and, therefore, this charge will not all be affected by the electrical fields near the semiconductor pn junction separating the device drain region from the well.
Even so, radiation particle impingement on a reverse-bias drain region of either an n-channel or p-channel MOSFET, with the resulting reduction in the associated reverse-bias voltage, poses a risk of a logic state change at circuit nodes to which same is connected. If the circuit involved is a D-type flip-flop with a feedback loop arrangement, such a voltage reduction can be propagated around the feedback arrangement before the reverse-bias voltage across the affected drain-substrate junction involved has sufficiently recovered its former voltage value. As a result, a new logic state could be established and maintained in the feedback loop arrangement.
Such a result can be substantially prevented by use of the feedback logic gate circuit arrangement disclosed in the copending application indicated above which is hereby incorporated herein. As described there, the cross-coupled transistor load logic gate circuitry subject to certain conditions can prevent the establishment of such a logic change due to a radiation particle impingement along the feedback path of such a feedback logic gate arrangement serving as a data latch. However, the effects of radiation particle impingement on circuitry external to such a feedback logic gate arrangement is not protected against unless this external circuitry is fully implemented using also only cross-coupled transistor load logic gate circuits. Thus, the data input signal circuitry with a clock signal input circuitry to the latch, suffering a radiation particle impingement therein, may lead to the introduction of incorrect logic states into the feedback loop.
Thus, a data latch which is resistant to establishing erroneous logic states therein due to errors in the data signals or clock signals supplied thereto would be desirable as this would allow supplying such signals from circuitry implemented using logic gate circuits other than cross-coupled transistor load logic gate circuits. Further, such a data latch should protect against transient logic state changes occurring therein being established as erroneous logic states in the latch.